1. Field of the Invention
The present invention relates to data detection, and more particularly, to a data detector for improving performance in maximum likelihood detection, and a method therefor.
2. Description of the Related Art
Signal processing technology relating to partial response maximum likelihood (PRML) decoding, including a Viterbi decoding process, has been applied to increase recording density without a drastic change in the characteristics of a conventional recording/reproducing apparatus. Many devices for implementing such technology have been suggested.
FIG. 1 is a block diagram showing the recording/reproducing unit of a digital videocassette recorder (VCR) having a partial response (PR) 4 (+1,0,-,1) type. In FIG. 1, input data to be recorded is modulated by a precoder 102. That is, the output of an adder 104 of the precoder 102 is delayed by a time corresponding to 2 bits of the input data, by two unit delays (D) 106 and 108, and then fed back to the adder 104. The adder 104 performs an exclusive OR operation on the input data and the feedback data. Such operation of the precoder 102 converts the input data into an interleaved non-return to zero inversion (NRZI) data. Here, D represents a unit delay corresponding to 1 bit of the input data.
A recording amplifier 110 is current driven and flows enough current through a recording head HD1 of a channel 112 such that data is recorded on a recording medium T in an optimal state. A signal reproduced by a reproducing head HD2 of the channel 112 is amplified to a desired amplitude by a playback amplifier 114. Then, an equalizer 116 compensates for distortion in the waveform and amplitude of the reproduced signal. The compensation involves removing a DC component and transmitting only a high frequency component which indicates transition of record data as a differential type pulse, due to a differential characteristic of the channel 112. Here, the reproduced signal output from the playback amplifier 114 after being amplified is a PR(+1,-1) type signal.
The differential type channel characteristic corresponds to a (1-D) characteristic. A channel demodulator 118 having a (1+D) integral characteristic converts the PR(+1,-1) type signal output from the equalizer 116 into a PR4(+1,0,-1) type signal, so that the signal modulated by the precoder 102 of a recorder is demodulated into the original record data. Here, the channel demodulator 118 includes a delay 120 for delaying the output of the equalizer 116 by a unit bit (1 bit), and an adder 122 for adding a signal delayed by the delay 120 to the output of the equalizer 116. A clock generator 124 detects timing of the reproduced signal equalized by the equalizer 116 using an internal phase locked loop (PLL) circuit to generate a clock signal required for a data detector 126.
The data detector 126 further includes an analog-to-digital converter (ADC) 128 and a digital Viterbi decoder 130. The ADC 128 converts the output of the channel demodulator 118 into digital data according to a sampling clock signal generated by a clock generator 124, and the digital Viterbi decoder 130 decodes the digital data using a Viterbi decoding algorithm, which is a maximum likelihood decoding algorithm, according to a driving clock signal generated by the clock generator 124. In the ideal case, a sampling point of the ADC 128 corresponds to a detection point for the reproduced data, the sampling point being a critical factor for determining the performance of the digital Viterbi decoder 130. However, the conventional data detector 126 shown in FIG. 1 cannot process a continuously varying signal, so a phase error occurs between the sampling point and the actual optimal detection point. As a result, Viterbi decoding performance is lowered.